Dual-Edge Triggered Lightweight Implementation of AES for IoT Security

23rd International Symposium, VDAT 2019, Indore, India, July 4–6, 2019, Revised Selected Papers

Document identifier: oai:DiVA.org:ltu-75978
Access full text here:10.1007/978-981-32-9767-8_26
Keyword: Engineering and Technology, Electrical Engineering, Electronic Engineering, Information Engineering, Other Electrical Engineering, Electronic Engineering, Information Engineering, Teknik och teknologier, Elektroteknik och elektronik, Annan elektroteknik och elektronik, Lightweight, Dual-edge triggered, AES Architecture, IoT, Security, Elektroniksystem, Electronic systems
Publication year: 2019
Relevant Sustainable Development Goals (SDGs):
SDG 9 Industry, innovation and infrastructure
The SDG label(s) above have been assigned by OSDG.ai

Abstract:

Internet of Things (IoT) is now a growing part of our life. More than 10 billion devices are already connected, and more are expected to be deployed in the next coming years. To provide a practical solution for security, privacy and trust is the main concern for deploying IoT in such a large scale. For security and privacy in IoT, cryptography is the required solutions. AES algorithm is a well known, highly secure and symmetric key algorithm, but the area and power budget of AES makes it unsuitable for IoT Security. In this paper, we have presented a lightweight implementation of AES, with dual-edge triggered S-box. The proposed architecture has been implemented on FPGA as well as in ASIC on 180 nm technology. The proposed architecture uses a 32-bit data path to encrypt 128-bit plain-text with 128-bit cipher-key. ASIC implementation of the proposed architecture results in low-power (122.7 μ" role="presentation" style="box-sizing: border-box; display: inline-table; line-height: normal; letter-spacing: normal; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; max-height: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative;">μμW at 1 V) consumption with a reduction in the hardware overhead by 30% and a throughput of 23 Mbps at 10 MHz clock frequency.

Authors

Sajid Khan

Nanoscale Devices, VLSI Circuit and System Design Lab, Discipline of Electrical Engineering, Indian Institute of Technology Indore, Indore, India
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Neha Gupta

Nanoscale Devices, VLSI Circuit and System Design Lab, Discipline of Electrical Engineering, Indian Institute of Technology Indore, Indore, India
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Abhinav Vishvakarma

Nanoscale Devices, VLSI Circuit and System Design Lab, Discipline of Electrical Engineering, Indian Institute of Technology Indore, Indore, India
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Shailesh Singh Chouhan

Luleå tekniska universitet; EISLAB
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Jai Gopal Pandey

Integrated Systems Group, CSIR- Central Electronics Engineering Research Institute (CEERI)Pilani, India
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Santosh Kumar Vishvakarma

Nanoscale Devices, VLSI Circuit and System Design Lab, Discipline of Electrical Engineering, Indian Institute of Technology Indore, Indore, India
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