Analyzing Design Parameters of Nano-Magnetic Technology Based Converter Circuit

23rd International Symposium, VDAT 2019, Indore, India, July 4–6, 2019, Revised Selected Papers

Document identifier: oai:DiVA.org:ltu-75976
Access full text here:10.1007/978-981-32-9767-8_4
Keyword: Engineering and Technology, Electrical Engineering, Electronic Engineering, Information Engineering, Other Electrical Engineering, Electronic Engineering, Information Engineering, Teknik och teknologier, Elektroteknik och elektronik, Annan elektroteknik och elektronik, Nano-magnetic logic, Binary-to-gray converter, Magnetic anisotropy, Minority voter, Perpendicular nano-magnetic logic, Elektroniksystem, Electronic systems
Publication year: 2019
Relevant Sustainable Development Goals (SDGs):
SDG 9 Industry, innovation and infrastructure
The SDG label(s) above have been assigned by OSDG.ai

Abstract:

Digital circuits need improvement in computation speed, reducing circuit complexity and power consumption. Emerging Technology NML can be such an architecture at nano-scale and thus emerges as a viable alternative for the digital CMOS VLSI. This technology has the capability to compute the logic as well as storage into the same device, which points out that it great potential for emerging technology. Since Nano-magnetic, technology fast approaches its minimal feature size, high device density and operate at room temperature. NML based circuits synthesis has to opt for novel half subtraction and Binary-to-Gray architecture for achieving minimal complexity and high-speed performance. This manuscript pro-poses area efficient binary half-subtraction and Binary-to-Gray converter architecture. Circuits’ synthesize are performed by MagCAD tool and simulate by Modelsim simulator. The circuit’s performance are estimated over other existing designs. The proposed converter consume 73.73%, and 94.49% less area than the converter designed using QCA and CMOS technique respectively. This is a significant contribution to this paper. Simulation results of converter show that the critical path delay falls within 0.15 µs.

Authors

Bandan Kumar Bhoi

Department of Electronics and Telecommunication, Veer Surendra Sai, University of Technology, Burla, India
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Neeraj Kumar Misa

Department of Electronics and Communication Engineering, Bharat Institute of Engineering and Technology, Hyderabad, India
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Shailesh Singh Chouhan

Luleå tekniska universitet; EISLAB
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Sarthak Acharya

Luleå tekniska universitet; EISLAB
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